Demand on the global market for higher integration motivates the requirement for high count multi-channel synchronization devices, mainly PLLs. Different applications require a different number of channels. Using devices with more than the required number of channels is often the case, with obvious cost disadvantage. Distributing functions over one master device and multiple slave devices is an option, but it is not one that can be widely used due to lack of good synchronization, which requires lots of feedback connection clocks from each slave device to the master device.
One prior art solution uses a high integration multi-channel PLL device that can manage the highest demand for number of channels often over 10 to cover applications that do not require as many channels. The requirement for high silicon and board area makes this solution less and less attractive. Another prior art solution employs devices with a small number of PLL channels to cover all required applications. The disadvantages of this solution are technical difficulties of proper synchronization and output clock alignment among the used PLL devices, as well as overhead of complex digital PLL functions in each device, which usually equates to a higher price.
Another solution builds an entire portfolio of multi-channel PLL devices with all the required possible channel counts. The cost disadvantage of this option is evident.
Yet another solution uses a master-slave concept of dispersing area intensive and performance critical functions into slave devices. The problem with this prior solution was lack of a good synchronization method, which assumed the use of an external feedback concept similar to a numerically controlled oscillator (NCO), where frequency and phase errors were corrected by feedback clocks from slave devices to the master device. As a result the design is too complex, and uses too many resources in form of pins on the master device and slave devices, as well as other slave resources such as output dividers.
The use of a master-slave concept with direct control of the slaves by the master has also been tried, but this involves strict timing closure requirements that are impractical or impossible to implement in multi-chip or even a multi-die environment.